tegwick 19e80cc9bc CYA-WP-0005 T02 done (ralph iter 2): Formalize Profile 0 baseline everywhere ... - MemoryVision.md: Large new 'Profile 0 Baseline (Post-0003 / Current Shipped)' section with exact ports, activation logic, retrospection, safety invariants, usage sites, and relationship to 1–3 (plus the prior research section from T01). - src/cya/memory/__init__.py: Updated module docstring to declare Profile 0 reality + references to MemoryVision + CYA-WP-0005. - src/cya/orchestrator.py: Updated docstring with Profile 0 memory wiring note. - SCOPE.md: Named Profile 0 explicitly in delivered slices and core capabilities. - tests/test_memory.py: Added two new explicit 'Profile 0' tests + comments asserting provenance markers, kinds, activation_context support (T02 acceptance). - README.md + AGENTS.md: Added Profile 0 mentions + links to the workplan. All T02 acceptance criteria met. Ralph loop active. Next: T03 (full Profiles 1–3 definitions + matrix).		2026-05-27 20:01:51 +02:00
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CYA-WP-0001-console-native-mvp.md	docs(memory): add MemoryVision.md + gap analysis and related doc updates	2026-05-26 02:42:54 +02:00
CYA-WP-0002-memory-integration-roadmap.md	chore(docs+tests): complete T05 + T06 for CYA-WP-0002. All 6 tasks done. README Memory section, AGENTS update, full test coverage for real memory + safety. Workplan retired.	2026-05-26 07:01:12 +02:00
CYA-WP-0003-contextual-memory-activation-and-retrospection.md	chore(workplan): mark CYA-WP-0003 as fully done (frontmatter status: done)	2026-05-26 20:30:12 +02:00
CYA-WP-0004-dev-install-and-release-packaging.md	chore(workplan): mark CYA-WP-0004 as fully done (frontmatter status: done)	2026-05-27 00:19:13 +02:00
CYA-WP-0005-agentic-memory-profiles-and-phase-memory-feedback.md	CYA-WP-0005 T02 done (ralph iter 2): Formalize Profile 0 baseline everywhere	2026-05-27 20:01:51 +02:00